The present invention generally relates to semiconductor processing, and in particular to a system for monitoring inter layer dielectric deposition.
In the semiconductor industry, there is a continuing trend toward higher device densities. To achieve these higher densities, efforts continue toward scaling down device dimensions (e.g., at sub-micron levels) on semiconductor wafers. To accomplish such high device packing densities, smaller and smaller feature sizes are required. This may include the width and spacing of interconnecting lines, spacing and diameter of contact holes, and the surface geometry such as comers and edges of various features. Similarly, finer and more uniform layers of inter layer dielectrics (hereinafter ILDs) are required to separate such features. For reasons that will be described below, void formation in the ILDs should be mitigated and/or prevented.
The process of manufacturing semiconductors, or integrated circuits (commonly called ICs, or chips) typically consists of more than a hundred steps, during which hundreds of copies of an integrated circuit may be formed on a single wafer. Generally, the process involves creating several patterned layers on and into the substrate that ultimately forms the complete integrated circuit This layering process creates electrically active regions in and on the semiconductor wafer surface. To isolate the active regions or layers, ILDs are typically formed over them.
In most conventional IMD deposition processes, chemical vapor deposition is performed, where a solid film of oxide is formed on a substrate by the reaction of an oxide gas and the substrate. Various parameters such as the oxide source and deposition method influence the characteristics of the resulting ILD. In chemical vapor deposition, gas mixture, temperature, RF power, pressure and gas flow rare, among other factors, may be varied to achieve the desired characteristics.
Undesired fluctuations in any one or a combination of these parameters may lead to void formation in the ILD. In many current applications, ILD formation must conform to exacting specifications in order to mitigate or prevent void formation. A void present in the ILD may cause electrical shorting (short circuits), cracking in the circuit, and/or lead to an open circuit depending on the size and location of the void. For example, voids which exceed about 25% of a structure width and/or are higher than the structure surface in height tend to cause any one or a combination of these problems. Voids which are formed early on in the semiconductor fabrication process but are undetected until further processing has been done may exacerbate or cause even more problems, resulting in an inoperable device.
With the requirement of smaller and smaller features and higher device densities, detection and mitigation of void formation is even more critical to the fabrication of operable and effective semiconductor devices. Thus, to detect the formation of voids, including their size and number, an efficient system/method to monitor ILD deposition for void formation and detection is desired to increase the reliability and performance of semiconductor devices.
The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an extensive overview of the invention. It is intended to neither identify key or critical elements of the invention nor delineate the scope of the invention. Its sole purpose is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.
The present invention provides for a system that facilitates controlling inter layer dielectric (hereinafter xe2x80x9cILDxe2x80x9d) deposition and detecting void formation in the ILD via scatterometry. Scatterometry is a technique that involves directing a light beam, typically a laser, on an area to be characterized and measuring the angular distribution of the light that is elastically scattered from that area An exemplary system may employ one or more light sources arranged to project light on respective portions of an ILD layer and one or more light detecting devices to collect light reflected by the ILD and/or light passing through the ILD. The light reflected from the ILD is indicative of the presence of voids in the ILD. The presence of ILD voids is monitored and detected by the system, and semiconductor devices with ILD voids may be marked for further processing and/or discarded. As a result, fewer semiconductors and integrated circuit chips with ILD voids are produced.
One particular aspect of the invention relates to a system for detecting and monitoring ILD void formation. A system for directing light directs light to a portion of the ILD, and a measuring system measures parameters of the ILD based on light reflected from the ILD. A processor is operatively coupled to the measuring system, and receives ILD parameter data from the measuring system. By comparing the collected parameter data with a database comprised of known ILD layers, each having at least one void present, the processor uses the collected data to detect and monitor void formation in the ILD.
Yet another aspect of the present invention relates to a method for detecting and monitoring ILD void formation. The method comprises defining an ILD layer as a plurality of portions and then directing light onto at least one of the portions. Light reflected from the at least one portion is collected and analyzed to determine whether there are voids in the at least one portion. If void formation is detected in the at least one portion, such void formation may be monitored to determine the extent and dimensions of the void and/or selectively marked to be discarded.
Still another aspect of the present invention relates to a system for detecting and monitoring ILD void formation including a means for directing light onto a plurality of portions of an ILD layer, a means for collecting light from the respective ILD layer portions and a means for analyzing the collected light to determine whether there is void formation in the respective ILD layer portions.
To the accomplishment of the foregoing and related ends, the invention, then, comprises the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative embodiments of the invention. But these embodiments are indicative of only a few of the various ways in which the principles of the invention may be employed. Other objects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.